1. Technical Field
The present invention generally relates to semiconductor design technology, and more particularly, to an output enable (OE) signal generation circuit of a semiconductor memory device.
2. Related Art
A semiconductor memory device internally uses an internal clock signal to output data. However, a semiconductor memory device requires an external clock signal to output data to the outside during a read operation. Therefore, during the read operation, the semiconductor memory device must perform an operation that synchronizes a read command, an external clock signal, and an internal clock signal. For this occur, there will be an instance where the clock signal synchronized with the read command transitions from the external clock signal to the internal clock signal, which is commonly referred to as “domain crossing.”
The semiconductor memory device includes various circuits to perform the domain crossing operation, such as an output enable (hereinafter, “OE”) signal generation circuit. The OE signal generation circuit synchronizes a read command, which is transmitted in synchronization with an external clock signal, with an internal clock signal and outputs the synchronized signal as an OE signal. The OE signal subjected to the domain crossing operation includes CAS latency (CL) information, which allows the semiconductor memory device to output data in synchronization with an external clock signal at a desired time after the read command.
The CL information may be measured from when a read command is applied to when data is to be outputted, using one cycle of an external clock signal as the unit time, and is generally stored in a mode register set (MRS) provided inside a semiconductor device.
Skew may occur between the external clock signal and the internal clock signal, due to delay elements inside the semiconductor memory device. The semiconductor memory device includes an internal clock signal generation circuit to compensate for the skew. It representatively includes a phase locked loop (PLL) and a delay locked loop (DLL). In embodiments of the present invention, a DLL clock signal generated by the DLL is used as an internal clock signal.
FIG. 1 illustrates a conventional DLL circuit 200.
Referring to FIG. 1, a DLL locking signal DLL_LOC will be described as follows.
The DLL circuit 200 includes a DLL delay line 210, a DLL replica model unit 230, and a phase detection unit 220.
The DLL delay line 210 is configured to delay an external clock signal EXTCLK by a predetermined time and outputs a DLL clock signal DLLCLK. The DLL replica model unit 230 models a delay until the DLL clock signal DLLCLK is outputted to the outside of the semiconductor memory device, and is configured to further delay the DLL clock signal DLLCLK by a predetermined time and output a feedback clock signal FBCLK. The feedback clock signal FBCLK includes information on the delay of the DLL delay line 210 and the delay until the DLL clock signal DLLCLK is outputted to the outside of the semiconductor memory device.
The phase detection unit 220 is configured to compare the phases of the external clock signal EXTCLK with the feedback clock signal FBCLK, and enable the DLL locking signal DLL_LOC when the phases coincide with each other. When the DLL locking signal DLL_LOC is enabled, the DLL delay line applies a delay on the external clock signal EXTCLK. When a DLL reset signal DLLRST is enabled, the phase detection unit 220 disables the DLL locking signal DLL_LOC such that the DLL circuit 200 resets the delay on the DLL delay line 210.
When the DLL locking signal DLL_LOC is enabled, the DLL circuit 200 delays the external clock signal EXTCLK by the fixed delay and outputs the DLL clock signal DLLCLK, before an operation of the DLL circuit 200 is reset. When the DLL reset signal DLLRST is enabled in a DLL reset mode, the DLL locking signal DLL_LOC is disabled to reset the delay on the DLL delay line 210.
FIG. 2 is a block diagram of a conventional OE signal generation circuit 1.
Referring to FIG. 2, the OE signal generation circuit 1 includes an OE reset signal generation unit 10, a first delay unit 20, a second delay unit 30, a counter unit 40, and an OE signal output unit 50. The first delay unit 20 includes a delay line 21 and a replica model section 22.
The OE reset signal generation unit 10 is configured to enable an OE reset signal OERST in response to a reset signal RST or DLL locking signal DLL_LOC. The reset signal RST is enabled in response to a setting operation of an MRS of the semiconductor memory device.
In order to compensate for delay caused by delay elements inside a semiconductor memory device, a DLL circuit generates a DLL clock signal DLLCLK having a phase which leads that of an external clock signal by a predetermined time such that the clock signal is precisely synchronized with data. The DLL circuit works with the semiconductor memory device and adjusts the delay for the clock signal. Depending on the state of the semiconductor memory device, the operation thereof may need to be reset to recover the initial delay time. For this reset operation, the DLL reset mode applies a predetermined delay to a clock signal inputted to the delay line of the DLL circuit.
The DLL locking signal DLL_LOC fixes a delay value inside the DLL circuit when the DLL clock signal DLLCLK has a phase which leads the phase of the external clock signal EXTCLK by the predetermined time, and is disabled when the DLL reset mode is enabled. When the DLL locking signal DLL_LOC is disabled, the OE reset signal generation unit 10 enables an OE reset signal OERST.
The delay line 21 of the first delay unit 20 models a delay line which delays the external clock signal by a predetermined time in the DLL circuit, and is configured to delay the OE reset signal OERST by a predetermined time and outputs a first delayed OE reset signal D1.
The replica model section 22 of the first delay unit 20 models a delay inside the semiconductor memory device until a signal outputted from the DLL circuit is outputted to the outside of the semiconductor device. The replica model section 22 is configured to delay the first delayed OE reset signal D1 by a predetermined time and output a second delayed OE reset signal D2.
The second delay unit 30 models the delay line which delays an external clock signal by a predetermined time in the DLL circuit, and is configured to delay a read command RD by a predetermined time and output the delayed read command DRD. The second delay unit 30 delays the read command RD by the same delay as that of the delay line 21 of the first delay unit 20.
The counter unit 40 is configured to count the external clock signal EXTCLK and output a count value N, in response to the OE reset signal OERST and the second delayed OE reset signal D2. The count value N represents a signal delay caused by the first delay unit 20.
The OE signal output unit 50 is configured to shift the delayed read command DRD by the CL-count value N (CL-N) in synchronization with the DLL clock signal DLLCLK, and output an OE signal OE.
Therefore, the OE signal OE is enabled by the delay of the replica model section 22 before the CL. The semiconductor memory device uses the OE signal OE to output data in synchronization with the external clock signal at a desired time after the read command.
The OE signal generation circuit 1 enables the DLL reset mode and the OE reset signal OERST to set the count value N, according to the reset signal RST set in the MRS.
Therefore, the OE signal generation circuit 1 may not secure an accurate count value N when the frequency of the external clock signal EXTCLK is changed, which may lead to undesired timing consequences. The output timing of the OE signal OE may not be secured except by utilizing a reset method using the DLL reset mode or MRS.